Hardware Security

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Hardware security covers a broad range of topics from trusted computing to Trojan circuits. To classify these topics we follow the different hardware abstraction layers as introduced by the Y-chart of Gajski & Kuhn. The different layers of the hardware design process will be introduced in section 1. It is linked with the important concept of a root of trust and associated threat models in the context of hardware security. Next follows section 2 on measuring and evaluating hardware security. The next sections gradually reduce the abstraction level. Section 3 describes secure platforms, i.e. a complete system or system-on-chip as trusted computing base. Next section 4 covers hardware support for software security: what features should a programmable processor include to support software security. This section is closely related to the Software Security CyBOK Knowledge Area [1]. Register transfer level is the next abstraction level down, covered in section 5. Focus at this level is typically the efficient and secure implementation of cryptographic algorithms so that they can be mapped on ASIC or FPGA. This section is closely related to the Cryptography CyBOK Knowledge Area [2]. All implementations also need protection against physical attacks, most importantly against side- channel and fault attacks. Physical attacks and countermeasures are described in section 6. Section 7 describes entropy sources at the lowest abstraction level, close to CMOS technology. It includes the design of random numbers generators and physically unclonable functions. The last technical section describes aspects related to the hardware design process itself. This chapter ends with the conclusion and an outlook on hardware security.